This invention relates to a sample rate conversion system having an interpolation function and, more particularly, to a sample rate conversion circuit (to be referred to hereinafter as an SRC) for converting first digital data having a first clock frequency into second digital data having a second clock frequency, which is suitable for use in a digital data conversion system which can demodulate a television signal by means of digital processing.
In recent times, a technique has been developed for digitally processing a video signal within a television receiver. Development of this technique has taken place because even though a signal processing circuit for performing analog signal processing can be integrated in a single-chip LSI (Large Scale Integrated circuit), the LSI requires a large number of peripheral components and some of these components must be adjusted, thus making it difficult to reduce the price of the circuit. In order for image quality to be improved, a memory for delaying the video signal must be provided, and various filtering operations must be performed. In this regard, a digital circuit can more precisely and stably perform such processing than can an analog circuit. A signal processing section is effective in a digital circuit for separating a composite video signal into a luminance signal and chrominance signals, and demodulating these signals in a digital circuit.
With the NTSC scheme, a chrominance signal is quadrature-modulated by a chrominance subcarrier of frequency fsc. The chrominance subcarrier of fsc is phase-inverted for every line (every scanning line), and a difference between adjacent scanning lines can be calculated, to separate a modulated signal from a composite color video signal. The modulated signal is then synchronously detected by the chrominance subcarrier of fsc, so as to demodulate a chrominance signal.
In order to demodulate a quadrature-modulated signal, the SIN component and the COS component of the carrier are multiplied together to obtain a demodulated output. If sampling is performed using 4fsc clocks in accordance with the digital scheme, the demodulated output can then be obtained by means of simple filtering processing. Therefore, in the case of a system for obtaining demodulated outputs of I- and Q-axes, the use of the 4fsc clocks is very important.
In the case where a color video signal is processed digitally, scanning line interpolation can then be advantageously performed. When the NTSC scheme is utilized, a 2:1 interlacing scheme is employed, in which scanning lines for one image are thinned out and then transmitted. While this scheme is advantageous as regards compressing a transmission it does, however, result in degradation of image quality--the so-called interlace problem. A typical example of such image quality degradation is the occurrence of line flickering, where a still image flickers vertically. This can be prevented by use of scanning line interpolation where, more specifically, the thinned-out scanning lines are interpolated so that an image is reproduced and displayed as a so-called non-interlacing scheme, thereby preventing flickering. Scanning line interpolation, requires the use of a two- or three-dimensional filter. Such a filter can be operated more easily by the digital technique, than by the analog technique.
When sampling is performed using the 4fsc clocks, as described above, the number of clocks required for sampling a 1H (one horizontal scanning period) signal is 910 in the case of the NTSC video signal. In other words, for proper scanning line interpolation to be performed, in this instance, 910 clocks must always be present during one horizontal scanning period. For this purpose, a 910 fh (fh indicates a horizontal frequency) clock generator is used, and improvements to the generator must be carried out so that the oscillation frequency of the generator can be changed to follow a horizontal sync signal.
As has been described above, clocks of frequency 4fsc are necessary in order to demodulate chrominance signals, and scanning line interpolation requires clocks of a frequency of 910 fh. Therefore, in order that a system can be provided which can perform both chrominance demodulation and scanning line interpolation by way of digital processing, independent digital processing sections must be arranged in accordance with differences in the respective clock frequencies.
If a system is to be created which can perform both the above-mentioned chrominance demodulation and scanning line interpolation by means of a series of processing steps, this requires at a minimum, the provision of a D/A converter and an A/D converter each of a different clock frequency, i.e., as a 4fsc clock system and as a 910 fh clock system, which results in a system of high cost. When D/A conversion and A/D conversion are performed sequentially, this may degrade signals to be converted. In addition, since separate circuits are required for three systems, i.e., luminance, I-axis, and Q-axis components, this further increases the system cost.
Therefore, as regards a digital television receiver which demodulates digital video data, then reproduces and displays demodulated digital, video data, there is an urgent requirement for the development of an inexpensive system in which signal degradation does not occur. For a system to be realized which fulfills the above requirement, it is necessary that independent digital processing sections not be arranged depending on differences in individual clock frequencies, but instead be directly coupled digitally and use signals of the same operating frequency so as to exchange data.
The digital data sampling rate must be converted so as to allow direct data exchange between the two digital data processing systems having different operating frequencies. In order that sample rate conversion can be executed properly, however, a technique suitable for processing digital data of specific properties must be employed.